1. Field of the Invention
The present invention relates in general to semiconductor memory devices, and more particularly to a circuit and method for initializing a reference memory cell, in which the reference memory cell is very accurately initialized within a minimized period of time.
2. Description of the Prior Art
FIG. 1 is a circuit diagram of a reference memory cell initialization circuit based on a conventional first method. In this drawing, the reference numeral 10 denotes a main memory cell and the reference numeral 17 denotes a reference memory cell. Each of the main and reference memory cells 10 and 17 comprises a source, drain, control gate and floating gate.
A first load 11 is connected between the drain of the main memory cell 10 and a supply voltage source VCC, and a second load 12 is connected between the drain of the reference memory cell 17 and the supply voltage source VCC.
A comparator 13 inputs a first signal on the drain of the reference memory cell 17 at its first signal input terminal, or non-inverting input terminal, and a second signal on the drain of the main memory cell 10 at its second signal input terminal, or inverting input terminal, and then compares the inputted first and second signals with each other. The second signal is provided for reference and the first signal is provided for testing.
A programming controller 16 is provided to block an external path in a programming mode of the reference memory cell 17. A first switch S115 is connected to the drain of the reference memory cell 17 to control its connections to the programming controller 16 and the second load 12 in the programming mode of the reference memory cell 17 and a read mode thereof.
A second switch S218 is operated to apply a signal from a VPGM source to the gate of the reference memory cell 17 in the programming mode and a signal from a VREF source to the gate of the reference memory cell 17 in the read mode.
The operation of the first method-based reference memory cell initialization circuit with the above-mentioned construction will hereinafter be described.
The first method is to initialize the reference memory cell 17 by performing programming/programming verification operations. Reference current for the programming verification operation is generated from the main memory cell 10.
In order to program the reference memory cell 17, the first switch 15 connected to the drain of the reference memory cell 17 is directed to the programming controller 16, and the second switch 18 connected to the gate of the reference memory cell 17 is directed to the VPGM source. Under this condition, a programming pulse is applied to the reference memory cell 17 to program it.
If the programming of the reference memory cell 17 is completed, then the first switch 15 connected to the drain of the reference memory cell 17 is directed to the first signal input terminal of the comparator 13, and the second switch 18 connected to the gate of the reference memory cell 17 is directed to the VREF source. At this time, a signal VPCX is applied to the gate of the main memory cell 10.
As a result, currents flow respectively to the reference memory cell 17 and main memory cell 10. Here, the current flowing to the main memory cell 10 is defined as reference current and the current flowing to the reference memory cell 17 is defined as test current.
Voltages are generated across the first and second loads 11 and 12, respectively, because of the flow of the reference current and test current and then applied to the comparator 13. As a result, a difference between the currents flowing to the reference memory cell 17 and main memory cell 10 can be known from an output signal from the comparator 13.
If a threshold voltage of the main memory cell 10 is a known value, a threshold voltage of the reference memory cell 17 can be known on the basis of the above current difference. In the case where the current to the reference memory cell 17 is larger in value than that to the main memory cell 10, the first and second switches 15 and 18 are changed to the programming mode to advance the programming operation.
These programming/programming verification operations are repeated until the threshold voltage of the reference memory cell 17 enters into an allowable range.
FIG. 2 is a circuit diagram of a reference memory cell initialization circuit based on a conventional second method. In this drawing, the reference numeral 22 denotes a plurality of memory cells, each of which comprises a gate connected to a word line 23 and a drain connected to a bit line. An inverter is connected to the initial input of each of the word lines 23.
A selection transistor 25 is connected between a cascode device 26 and the drain of each of the memory cells 22 to connect a column load device 27 to a selected one of the memory cells 22. An inverter is connected between a gate and source of the cascode device 26 to invert a signal on the source and transfer the inverted signal to the gate.
Also, the reference numeral 29 denotes a plurality of reference memory cells, each of which comprises a source, drain, control gate and floating gate. Each of the reference memory cells 29 is connected to a reference column load device 32 via a corresponding selection device 30 and a cascode device 31. An inverter is connected between a gate and source of the cascode device 31 to invert a signal on the source and transfer the inverted signal to the gate.
A sense amplifier 28 is adapted to input a voltage signal at a contact node CN1 between the column load device 27 and the cascode device 26 at its SIN terminal and a voltage signal at a contact node CN2 between the column load device 32 and the cascode device 31 at its RIN terminal in a read mode. A switch SW is disposed between the contact node CN1 and the SIN terminal of the sense amplifier 28 to control the transfer of the voltage signal at the contact node CN1 to the SIN terminal. An NMOS transistor 36 is operated under control of a controller 34 to transfer the voltage signal at the contact node CN1 to a pad 35 when the switch SW is closed.
The sense amplifier 28 compares the voltage signal at the SIN terminal with that at the RIN terminal.
The floating gates of the reference memory cells 29 are programmed with different levels. A voltage switch 33 is provided to supply a charge pulse to the gate of each of the reference memory cells 29 until the reference memory cells 29 are programmed with different levels, namely, they store target charge amounts, respectively.
The controller 34 is adapted to control the voltage switch 33, selection device 30, NMOS transistor 36 and switch SW.
The operation of the second method-based reference memory cell initialization circuit with the above-mentioned construction will hereinafter be described.
The second method is to accurately set target threshold voltages of the reference memory cells according to characteristic curves of loads connected to reference memory cell bit lines and combine programming pulses into a plurality of groups upon programming the reference memory cells, so as to minimize time required in programming the reference memory cells up to the set target threshold voltages.
In other words, the second method first makes a programming pulse wide in width to move a threshold voltage of a specific reference memory cell to a target value at a large pace and then reduces the programming pulse width gradually as the threshold voltage of the reference memory cell approximates to the target value. Therefore, the second method is able to minimize the target threshold voltage arrival time while securing the accuracy at the maximum.
References for the above programming pulse combination and programming verification are set by the controller 34.
A specific reference memory cell is programmed and the programming verification operation is then performed to check whether a threshold voltage of the reference memory cell has arrived at a target value. If the threshold voltage of the reference memory cell has not arrived yet at the target value, the programming/programming verification operation are repeated until the threshold voltage of the reference memory cell arrives at the target value.
In other words, an accurate verification reference voltage is applied externally through the controller 34 to initialize one or more reference memory cells with difference threshold voltages, and a plurality of programming pulse combinations are used to reduce the entire programming time.
However, the above-mentioned conventional reference memory cell initialization circuits have the following disadvantages.
Firstly, the amount of implanted charge is verified whenever a programming pulse is supplied to a reference memory cell. As a result, a large amount of time is required in allowing a threshold voltage of the reference memory cell to arrive at a target value.
Secondly, a separate controller must be used to first make the programming pulse wide in width and then reduce the programming pulse width gradually as the threshold voltage of the reference memory cell approximates to the target value. The use of such a controller makes the entire construction complicated.
Thirdly, the resolution is within the range of the last pulse width.